The present invention relates to data processing systems, and more particularly, to the detection and correction of data errors in such systems.
In designing a system implemented in LSI (large scale integration), it has been found desirable to limit the number of different types of LSI chips within the system. The production of a mask to manufacture each LSI chip-type requires a large amount of design effort and expense in order to arrange the large number of components on the chip and to provide the connections on the chip between such components. Unless production costs are minimized by limiting the total number of different LSI chip-types, an LSI system is not cost competitive with systems implemented in MSI (medium scale integration) or SSI (small scale integration).
A problem associated with LSI chips is that a large number of input/output pins are often required because of the large number of circuit components and the input and output signals used in connection with such components. If the number of pins exceeds the maximum number which may be physically mounted on the chip, techniques are required for spreading functions or operations among several identical chips. Thus, in the case where several bytes of data are operated on at one time as a single data word, the data may be "sliced", for example in bytes, with an identical LSI data chip for receiving each byte in the data word and operating on each byte individually.
When a circuit for detecting or correcting data errors is implemented in LSI, it is desirable that the same circuit be capable of use at any location in the system where error detection or correction is needed. Furthermore, the circuit must also be capable of delivering control signals to each of the LSI data chips which receive slices of data so that each of the data chips may be constructed identically, even though they may be controlled individually.